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VLSID
2008
IEEE
142views VLSI» more  VLSID 2008»
15 years 10 months ago
Incorporating PVT Variations in System-Level Power Exploration of On-Chip Communication Architectures
With the shift towards deep sub-micron (DSM) technologies, the increase in leakage power and the adoption of poweraware design methodologies have resulted in potentially significa...
Sudeep Pasricha, Young-Hwan Park, Fadi J. Kurdahi,...
VTS
2008
IEEE
119views Hardware» more  VTS 2008»
15 years 10 months ago
Error Sequence Analysis
With increasing IC process variation and increased operating speed, it is more likely that even subtle defects will lead to the malfunctioning of a circuit. Various fault models, ...
Jaekwang Lee, Intaik Park, Edward J. McCluskey
VTS
2008
IEEE
83views Hardware» more  VTS 2008»
15 years 10 months ago
LS-TDF: Low-Switching Transition Delay Fault Pattern Generation
— Higher chip densities and the push for higher performance have continued to drive design needs. Transition delay fault testing has become the preferred method for ensuring thes...
Jeremy Lee, Mohammad Tehranipoor
VTS
2008
IEEE
77views Hardware» more  VTS 2008»
15 years 10 months ago
Test-Pattern Ordering for Wafer-Level Test-During-Burn-In
—Wafer-level test during burn-in (WLTBI) is a promising technique to reduce test and burn-in costs in semiconductor manufacturing. However, scan-based testing leads to significa...
Sudarshan Bahukudumbi, Krishnendu Chakrabarty
VTS
2008
IEEE
136views Hardware» more  VTS 2008»
15 years 10 months ago
Test-Pattern Grading and Pattern Selection for Small-Delay Defects
Timing-related defects are becoming increasingly important in nanometer technology designs. Small delay variations induced by crosstalk, process variations, powersupply noise, as ...
Mahmut Yilmaz, Krishnendu Chakrabarty, Mohammad Te...