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ISVLSI
2007
IEEE
121views VLSI» more  ISVLSI 2007»
15 years 10 months ago
Performance of Graceful Degradation for Cache Faults
In sub-90nm technologies, more frequent hard faults pose a serious burden on processor design and yield control. In addition to manufacturing-time chip repair schemes, microarchit...
Hyunjin Lee, Sangyeun Cho, Bruce R. Childers
ISVLSI
2007
IEEE
160views VLSI» more  ISVLSI 2007»
15 years 10 months ago
On the Limitations of Power Macromodeling Techniques
Although RTL power macromodeling is a mature research topic, it is not yet broadly accepted in the industrial environment. One of the main reasons impairing its widespread use as ...
Felipe Klein, Guido Araujo, Rodolfo Azevedo, Rober...
ISVLSI
2007
IEEE
127views VLSI» more  ISVLSI 2007»
15 years 10 months ago
Asymmetrically Banked Value-Aware Register Files
Designing high-performance low-power register files is of critical importance to the continuation of current performance advances in wide-issue and deeply-pipelined superscalar m...
Shuai Wang, Hongyan Yang, Jie Hu, Sotirios G. Ziav...
ISVLSI
2007
IEEE
121views VLSI» more  ISVLSI 2007»
15 years 10 months ago
Data Recovery Block Design for Impulse Modulated Power Line Communications in a Microprocessor
Power line communications (PLC) using impulse ultra wideband (UWB) in a microprocessor had been proposed for ubiquitous access of internal nodes for test/debug purposes. In this p...
Rajesh Thirugnanam, Dong Sam Ha, T. M. Mak
ISVLSI
2007
IEEE
230views VLSI» more  ISVLSI 2007»
15 years 10 months ago
A Methodology and Toolset to Enable SystemC and VHDL Co-simulation
The new design challenges imposed by the increasing difficulties of today’s electronic systems obligated designers to develop new methodologies. System-level design and Platfor...
Richard Maciel, Bruno Albertini, Sandro Rigo, Guid...