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ISVLSI
2007
IEEE
232views VLSI» more  ISVLSI 2007»
15 years 10 months ago
DSPstone Benchmark of CoDeL's Automated Clock Gating Platform
— We present a performance analysis of CoDeL, a highly efficient automated clock gating platform for rapidly developing power efficient hardware architectures. It automatically...
Nainesh Agarwal, Nikitas J. Dimopoulos
ISVLSI
2007
IEEE
205views VLSI» more  ISVLSI 2007»
15 years 10 months ago
An Automated Passive Analog Circuit Synthesis Framework using Genetic Algorithms
In this work, we present a genetic algorithm based automated circuit synthesis framework for passive analog circuits. A procedure is developed for the simultaneous generation of b...
Angan Das, Ranga Vemuri
ISVLSI
2007
IEEE
181views VLSI» more  ISVLSI 2007»
15 years 10 months ago
Code-coverage Based Test Vector Generation for SystemC Designs
Abstract— Time-to-Market plays a central role on System-ona-Chip (SoC) competitiveness and the quality of the final product is a matter of concern as well. As SoCs complexity in...
Alair Dias Jr., Diógenes Cecilio da Silva J...
ISVLSI
2007
IEEE
139views VLSI» more  ISVLSI 2007»
15 years 10 months ago
Automatic Retargeting of Binary Utilities for Embedded Code Generation
Contemporary SoC design involves the proper selection of cores from a reference platform. Such selection implies the design exploration of alternative CPUs, which requires the gen...
Alexandro Baldassin, Paulo Centoducatte, Sandro Ri...
VLSID
2007
IEEE
142views VLSI» more  VLSID 2007»
15 years 10 months ago
Novel Architectures for High-Speed and Low-Power 3-2, 4-2 and 5-2 Compressors
The 3-2, 4-2 and 5-2 compressors are the basic components in many applications, in particular partial product summation in multipliers. In this paper novel architectures and desig...
Sreehari Veeramachaneni, Kirthi M. Krishna, Lingam...