Sciweavers

2449 search results - page 413 / 490
» VLSI
Sort
View
VTS
2007
IEEE
116views Hardware» more  VTS 2007»
15 years 10 months ago
Case Study: Soft Error Rate Analysis in Storage Systems
Soft errors due to cosmic particles are a growing reliability threat for VLSI systems. In this paper we analyze the soft error vulnerability of FPGAs used in storage systems. Sinc...
Brian Mullins, Hossein Asadi, Mehdi Baradaran Taho...
FCCM
2007
IEEE
100views VLSI» more  FCCM 2007»
15 years 10 months ago
A Library and Platform for FPGA Bitstream Manipulation
— Since 1998, no commercially available FPGA has been accompanied by public documentation of its native machine code (or bitstream) format. Consequently, research in reconfigura...
Adam Megacz
ITNG
2007
IEEE
15 years 10 months ago
On Design and Analysis of a Feasible Network-on-Chip (NoC) Architecture
In this paper, we present several enhanced network techniques which are appropriate for VLSI implementation and have reduced complexity, high throughput, and simple routing algori...
Jun Ho Bahn, Seung Eun Lee, Nader Bagherzadeh
HPCC
2007
Springer
15 years 10 months ago
On Pancyclicity Properties of OTIS Networks
The OTIS-Network (also referred to as two-level swapped network) is composed of n clones of an n-node original network constituting its clusters. It has received much attention due...
Mohammad R. Hoseinyfarahabady, Hamid Sarbazi-Azad
DATE
2006
IEEE
124views Hardware» more  DATE 2006»
15 years 10 months ago
Timing-driven cell layout de-compaction for yield optimization by critical area minimization
This paper proposes a yield optimization method for standard-cells under timing constraints. Yield-aware logic synthesis and physical optimization require yield-enhanced standard ...
Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada