Sciweavers

2449 search results - page 421 / 490
» VLSI
Sort
View
SBCCI
2006
ACM
124views VLSI» more  SBCCI 2006»
15 years 5 months ago
A cryptography core tolerant to DFA fault attacks
This work describes a hardware approach for the concurrent fault detection and error correction in a cryptographic core. It has been shown in the literature that transient faults ...
Carlos Roberto Moratelli, Érika F. Cota, Ma...
ACSD
2005
IEEE
144views Hardware» more  ACSD 2005»
15 years 5 months ago
An Automated Fine-Grain Pipelining Using Domino Style Asynchronous Library
Register Transfer Level (RTL) synthesis model which simplified the design of clocked circuits allowed design automation boost and VLSI progress for more than a decade. Shrinking t...
Alexander B. Smirnov, Alexander Taubin, Ming Su, M...
CODES
2005
IEEE
15 years 5 months ago
System-level design automation tools for digital microfluidic biochips
Biochips based on digital microfluidics offer a powerful platform for massively parallel biochemical analysis such as clinical diagnosis and DNA sequencing. Current full-custom de...
Krishnendu Chakrabarty, Fei Su
DFT
2005
IEEE
109views VLSI» more  DFT 2005»
15 years 5 months ago
Hardware Testing For Error Tolerant Multimedia Compression based on Linear Transforms
In this paper, we propose a system-level error tolerance scheme for systems where a linear transform is combined with quantization. These are key components in multimedia compress...
In Suk Chong, Antonio Ortega
DFT
2005
IEEE
178views VLSI» more  DFT 2005»
15 years 5 months ago
Inter-Plane Via Defect Detection Using the Sensor Plane in 3-D Heterogeneous Sensor Systems
Defect and fault tolerance is being studied in a 3D Heterogeneous Sensor using a stacked chip with sensors located on the top plane, and inter-plane vias connecting these to other...
Glenn H. Chapman, Vijay K. Jain, Shekhar Bhansali