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VLSID
2005
IEEE
120views VLSI» more  VLSID 2005»
15 years 3 months ago
On Finding Consecutive Test Vectors in a Random Sequence for Energy-Aware BIST Design
During pseudorandom testing, a significant amount of energy and test application time is wasted for generating and for applying “useless” test vectors that do not contribute t...
Sheng Zhang, Sharad C. Seth, Bhargab B. Bhattachar...
ASPDAC
2005
ACM
127views Hardware» more  ASPDAC 2005»
15 years 3 months ago
Clock network minimization methodology based on incremental placement
: In ultra-deep submicron VLSI circuits, clock network is a major source of power consumption and power supply noise. Therefore, it is very important to minimize clock network size...
Liang Huang, Yici Cai, Qiang Zhou, Xianlong Hong, ...
ISLPED
2005
ACM
108views Hardware» more  ISLPED 2005»
15 years 3 months ago
Replacing global wires with an on-chip network: a power analysis
This paper explores the power implications of replacing global chip wires with an on-chip network. We optimize network links by varying repeater spacing, link pipelining, and volt...
Seongmoo Heo, Krste Asanovic
SBCCI
2005
ACM
123views VLSI» more  SBCCI 2005»
15 years 3 months ago
Fault tolerance overhead in network-on-chip flow control schemes
Flow control mechanisms in Network-on-Chip (NoC) architectures are critical for fast packet propagation across the network and for low idling of network resources. Buffer manageme...
Antonio Pullini, Federico Angiolini, Davide Bertoz...
SBCCI
2005
ACM
185views VLSI» more  SBCCI 2005»
15 years 3 months ago
Automatic generation of test sets for SBST of microprocessor IP cores
Higher integration densities, smaller feature lengths, and other technology advances, as well as architectural evolution, have made microprocessor cores exceptionally complex. Cur...
Ernesto Sánchez, Matteo Sonza Reorda, Giova...