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SBCCI
2005
ACM
111views VLSI» more  SBCCI 2005»
15 years 3 months ago
Total leakage power optimization with improved mixed gates
Gate oxide tunneling current Igate and sub-threshold current Isub dominate the leakage of designs. The latter depends on threshold voltage Vth while Igate vary with the thickness ...
Frank Sill, Frank Grassert, Dirk Timmermann
SBCCI
2005
ACM
115views VLSI» more  SBCCI 2005»
15 years 3 months ago
Design of a decompressor engine on a SPARC processor
Code compression, initially conceived as an effective technique to reduce code size in embedded systems, today also brings advantages in terms of performance and energy consumpti...
Richard E. Billo, Rodolfo Azevedo, Guido Araujo, P...
IWANN
2005
Springer
15 years 3 months ago
An Asynchronous 4-to-4 AER Mapper
In this paper, a fully functional prototype of an asynchronous 4-to-4 Address Event Representation (AER) mapper is presented. AER is an event driven communication protocol original...
Håvard Kolle Riis, Philipp Häfliger
SOFSEM
2005
Springer
15 years 3 months ago
Volumes of 3D Drawings of Homogenous Product Graphs
d Abstract) Lubomir Torok Institute of Mathematics and Computer Science Slovak Academy of Sciences Severna 5, 974 01 Banska Bystrica, Slovak Republic 3-dimensional layout of graph...
Lubomir Torok
ASPDAC
2004
ACM
96views Hardware» more  ASPDAC 2004»
15 years 3 months ago
Register binding and port assignment for multiplexer optimization
- Data path connection elements, such as multiplexers, consume a significant amount of area on a VLSI chip, especially for FPGA designs. Multiplexer optimization is a difficult pro...
Deming Chen, Jason Cong