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CHES
2004
Springer
170views Cryptology» more  CHES 2004»
15 years 3 months ago
Concurrent Error Detection Schemes for Involution Ciphers
Because of the rapidly shrinking dimensions in VLSI, transient and permanent faults arise and will continue to occur in the near future in increasing numbers. Since cryptographic c...
Nikhil Joshi, Kaijie Wu, Ramesh Karri
FPGA
2004
ACM
121views FPGA» more  FPGA 2004»
15 years 3 months ago
Highly pipelined asynchronous FPGAs
We present the design of a high-performance, highly pipelined asynchronous FPGA. We describe a very fine-grain pipelined logic block and routing interconnect architecture, and sh...
John Teifel, Rajit Manohar
GECCO
2004
Springer
15 years 3 months ago
Three Evolutionary Codings of Rectilinear Steiner Arborescences
A rectilinear Steiner arborescence connects points in the Euclidean plane’s first quadrant and the origin with directed rectilinear edges from the origin up and to the right. Th...
Bryant A. Julstrom, Athos Antoniades
GECCO
2004
Springer
15 years 3 months ago
Designing Multiplicative General Parameter Filters Using Adaptive Genetic Algorithms
Multiplicative general parameter (MGP) approach to finite impulse response (FIR) filtering introduces a novel way to realize cost effective adaptive filters in compact very large s...
Jarno Martikainen, Seppo J. Ovaska
HIPC
2004
Springer
15 years 3 months ago
Parallel Performance of Hierarchical Multipole Algorithms for Inductance Extraction
Parasitic extraction techniques are used to estimate signal delay in VLSI chips. Inductance extraction is a critical component of the parasitic extraction process in which on-chip ...
Hemant Mahawar, Vivek Sarin, Ananth Grama