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VTS
2002
IEEE
121views Hardware» more  VTS 2002»
15 years 2 months ago
Very Low Voltage Testing of SOI Integrated Circuits
Very Low Voltage (VLV) testing has been proposed to increase flaw detection in bulk silicon CMOS integrated circuits and this paper explores these and additional advantages in the...
Eric MacDonald, Nur A. Touba
VTS
2002
IEEE
109views Hardware» more  VTS 2002»
15 years 2 months ago
Controlling Peak Power During Scan Testing
This paper presents a procedure for modifying a given set of scan vectors so that the peak power during scan testing is kept below a specified limit without reducing fault coverag...
Ranganathan Sankaralingam, Nur A. Touba
VTS
2002
IEEE
113views Hardware» more  VTS 2002»
15 years 2 months ago
LI-BIST: A Low-Cost Self-Test Scheme for SoC Logic Cores and Interconnects
For deep sub-micron system-on-chips (SoC), interconnects are critical determinants of performance, reliability and power. Buses and long interconnects being susceptible to crossta...
Krishna Sekar, Sujit Dey
WACV
2002
IEEE
15 years 2 months ago
Monocular, Vision Based, Autonomous Refueling System
This paper describes design and implementation of a vision based platform for automated refueling tasks. The platform is an autonomous docking system in principle, with the specif...
Aly A. Farag, Emir Dizdarevic, Ahmed Eid, Albert L...
CASES
2009
ACM
15 years 2 months ago
Complete nanowire crossbar framework optimized for the multi-spacer patterning technique
Nanowire crossbar circuits are an emerging architectural paradigm that promises a higher integration density and an improved fault-tolerance due to its reconfigurability. In this...
M. Haykel Ben Jamaa, Gianfranco Cerofolini, Yusuf ...