Very Low Voltage (VLV) testing has been proposed to increase flaw detection in bulk silicon CMOS integrated circuits and this paper explores these and additional advantages in the...
This paper presents a procedure for modifying a given set of scan vectors so that the peak power during scan testing is kept below a specified limit without reducing fault coverag...
For deep sub-micron system-on-chips (SoC), interconnects are critical determinants of performance, reliability and power. Buses and long interconnects being susceptible to crossta...
This paper describes design and implementation of a vision based platform for automated refueling tasks. The platform is an autonomous docking system in principle, with the specif...
Aly A. Farag, Emir Dizdarevic, Ahmed Eid, Albert L...
Nanowire crossbar circuits are an emerging architectural paradigm that promises a higher integration density and an improved fault-tolerance due to its reconfigurability. In this...
M. Haykel Ben Jamaa, Gianfranco Cerofolini, Yusuf ...