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ICCAD
1998
IEEE
93views Hardware» more  ICCAD 1998»
15 years 2 months ago
Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation
This paper considers simultaneous gate and wire sizing for general very large scale integrated (VLSI) circuits under the Elmore delay model. We present a fast and exact algorithm w...
Chung-Ping Chen, Chris C. N. Chu, D. F. Wong
ICNP
1998
IEEE
15 years 2 months ago
A Lossless, Minimal Latency Protocol for Gigabit ATM Networks
Advances in ber-optic and VLSI technology have led to the emergence of very high-speed networks based on Asynchronous Transfer Mode ATM. The time required to transmit the data int...
Michael D. Santos, P. M. Melliar-Smith, Louise E. ...
IPPS
1998
IEEE
15 years 1 months ago
Hyper Butterfly Network: A Scalable Optimally Fault Tolerant Architecture
Boundeddegreenetworks like deBruijn graphsor wrapped butterfly networks are very important from VLSI implementation point of view as well as for applications where the computing n...
Wei Shi, Pradip K. Srimani
ISPD
1998
ACM
79views Hardware» more  ISPD 1998»
15 years 1 months ago
On wirelength estimations for row-based placement
Wirelength estimation in VLSI layout is fundamental to any pre-detailed routing estimate of timing or routability. In this paper, we develop e cient wirelength estimation techniqu...
Andrew E. Caldwell, Andrew B. Kahng, Stefanus Mant...
IH
1998
Springer
15 years 1 months ago
Fingerprinting Digital Circuits on Programmable Hardware
Advanced CAD tools and high-density VLSI technologies have combined to create a new market for reusable digital designs. The economic viability of the new core-based design paradig...
John Lach, William H. Mangione-Smith, Miodrag Potk...