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    ASAP
    2007
    IEEE
    153views Hardware» more  ASAP 2007»
    Performance Evaluation of Adaptive Routing Algorithms for achieving Fault Tolerance in NoC Fabrics
    14 years 9 months ago
    Performance Evaluation of Adaptive Routing Algorithms for achieving Fault Tolerance in NoC Fabrics
    Download  www.eecs.wsu.edu
    Commercial designs are integrating from 10 to 100 embedded functional and storage blocks in a single system on chip (SoC) currently, and the number is likely to increase significa...
    Haibo Zhu, Partha Pratim Pande, Cristian Grecu
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    CODES
    2008
    IEEE
    126views Software Engineering» more  CODES 2008»
    Methodology for multi-granularity embedded processor power model generation for an ESL design flow
    14 years 9 months ago
    Methodology for multi-granularity embedded processor power model generation for an ESL design flow
    Download  www.engr.colostate.edu
    With power becoming a major constraint for multi-processor embedded systems, it is becoming important for designers to characterize and model processor power dissipation. It is cr...
    Young-Hwan Park, Sudeep Pasricha, Fadi J. Kurdahi,...
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    ALGORITHMICA
    2006
    132views more  ALGORITHMICA 2006»
    Straight-Line Drawing Algorithms for Hierarchical Graphs and Clustered Graphs
    14 years 9 months ago
    Straight-Line Drawing Algorithms for Hierarchical Graphs and Clustered Graphs
    Download  www.cse.unsw.edu.au
    Hierarchical graphs and clustered graphs are useful non-classical graph models for structured relational information. Hierarchical graphs are graphs with layering structures; clus...
    Peter Eades, Qing-Wen Feng, Xuemin Lin, Hiroshi Na...
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    ENGL
    2008
    118views more  ENGL 2008»
    Hybrid Architecture of Genetic Algorithm and Simulated Annealing
    14 years 9 months ago
    Hybrid Architecture of Genetic Algorithm and Simulated Annealing
    Download  www.engineeringletters.com
    This paper discusses novel dedicated hardware architecture for hybrid optimization based on Genetic algorithm (GA) and Simulated Annealing (SA). The proposed architecture achieves ...
    Masaya Yoshikawa, Hironori Yamauchi, Hidekazu Tera...
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    CSUR
    2006
    147views more  CSUR 2006»
    A survey of research and practices of Network-on-chip
    14 years 9 months ago
    A survey of research and practices of Network-on-chip
    Download  www.ece.gatech.edu
    resents a perspective on existing NoC research. We define the following abstractions: system, network adapter, network, and link to explain and structure the fundamental concepts. ...
    Tobias Bjerregaard, Shankar Mahadevan
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