Abstract: Hybrid-redundant number representation has provided a flexible framework for digitparallel addition in a manner that facilitates area-time tradeoffs for VLSI implementati...
The miniaturization process of various sensing devices has become a reality by enormous research and advancements accomplished in Micro Electro-Mechanical Systems (MEMS) and Ve...
This paper presents a swarm intelligence based approach to optimally partition combinational CMOS circuits for pseudoexhaustive testing. The partitioning algorithm ensures reducti...
Ganesh K. Venayagamoorthy, Scott C. Smith, Gaurav ...
On-chip interconnection networks (OCINs) have emerged as a modular and scalable solution for wire delay constraints in deep submicron VLSI design. OCIN research has shown that the ...
Avinash Karanth Kodi, Ashwini Sarathy, Ahmed Louri
Abstract--Design of a suitable power gating (e.g., multithreshold CMOS or super cutoff CMOS) structure is an important and challenging task in sub-90nm VLSI circuits where leakage ...