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TCAD
2008
112views more  TCAD 2008»
14 years 8 months ago
A High-Performance Droplet Routing Algorithm for Digital Microfluidic Biochips
In this paper, we propose a high-performance droplet router for a digital microfluidic biochip (DMFB) design. Due to recent advancements in the biomicroelectromechanical system and...
Minsik Cho, David Z. Pan
JDA
2010
131views more  JDA 2010»
14 years 8 months ago
Convex drawings of hierarchical planar graphs and clustered planar graphs
: Hierarchical graphs are graphs with layering structures; clustered graphs are graphs with recursive clustering structures. Both have applications in VLSI design, CASE tools, soft...
Seok-Hee Hong, Hiroshi Nagamochi
DSD
2010
IEEE
137views Hardware» more  DSD 2010»
14 years 7 months ago
A C-to-RTL Flow as an Energy Efficient Alternative to Embedded Processors in Digital Systems
We present a high-level synthesis flow for mapping an algorithm description (in C) to a provably equivalent registertransfer level (RTL) description of hardware. This flow uses an ...
Sameer D. Sahasrabuddhe, Sreenivas Subramanian, Ku...
ICAI
2010
14 years 7 months ago
Constraint-Based Dogleg Channel Routing with Via Minimization
- In this article, we present an algorithm which is capable of transforming a gridded dogleg channel routing problem into a constraint programming (CP) problem. The transformed CP ...
I-Lun Tseng, Huan-Wen Chen, Che-I Lee, Adam Postul...
ICCAD
2010
IEEE
158views Hardware» more  ICCAD 2010»
14 years 7 months ago
Novel binary linear programming for high performance clock mesh synthesis
Clock mesh is popular in high performance VLSI design because it is more robust against variations than clock tree at a cost of higher power consumption. In this paper, we propose ...
Minsik Cho, David Z. Pan, Ruchir Puri