Clock network construction is one key problem in high performance VLSI design. Reducing the clock skew variation is one of the most important objectives during clock network synthe...
Linfu Xiao, Zigang Xiao, Zaichen Qian, Yan Jiang, ...
Abstract--Achieving fast, precise, and scalable fault localization has long been a highly desired feature in all-optical mesh networks. Monitoring tree (m-tree) is an interesting m...
As contemporary VLSI designs grow in complexity, design debugging has rapidly established itself as one of the largest bottlenecks in the design cycle today. Automated debug soluti...
The gap between VLSI technology and fabrication technology leads to strong refractive effects in lithography. Consequently, it is a huge challenge to reliably print layout features...
The continuous increase of leakage power consumption
in deep sub-micro technologies necessitates more aggressive
leakage control. Runtime leakage control (RTLC) is effective,
si...