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ICASSP
2011
IEEE
14 years 1 months ago
Design and implementation of cubic spline interpolation for spike sorting microsystems
Abstract—Accurate spike sorting is important for neuroscientific and neuroprosthetic applications. The sorting of spikes depends on the features extracted from the neural wavefo...
Tung-Chien Chen, Yun-Yu Chen, Tsung-Chuan Ma, Lian...
85
Voted
DAC
2011
ACM
13 years 9 months ago
AENEID: a generic lithography-friendly detailed router based on post-RET data learning and hotspot detection
In the era of deep sub-wavelength lithography for nanometer VLSI designs, manufacturability and yield issues are critical and need to be addressed during the key physical design i...
Duo Ding, Jhih-Rong Gao, Kun Yuan, David Z. Pan
106
Voted
DAC
2009
ACM
15 years 10 months ago
Exploring serial vertical interconnects for 3D ICs
Three-dimensional integrated circuits (3D ICs) offer a promising solution to overcome the on-chip communication bottleneck and improve performance over traditional two-dimensional...
Sudeep Pasricha
DAC
2009
ACM
15 years 10 months ago
A fully polynomial time approximation scheme for timing driven minimum cost buffer insertion
As VLSI technology enters the nanoscale regime, interconnect delay has become the bottleneck of the circuit timing. As one of the most powerful techniques for interconnect optimiz...
Shiyan Hu, Zhuo Li, Charles J. Alpert
82
Voted
DAC
2008
ACM
15 years 10 months ago
ELIAD: efficient lithography aware detailed router with compact post-OPC printability prediction
In this paper, we present ELIAD, an efficient lithography aware detailed router to optimize silicon image after optical proximity correction (OPC) in a correct-by-construction man...
Minsik Cho, Kun Yuan, Yongchan Ban, David Z. Pan