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VLSID
2001
IEEE
200views VLSI» more  VLSID 2001»
15 years 10 months ago
Evaluation of the Traffic-Performance Characteristics of System-on-Chip Communication Architectures
The emergence of several communication architectures for System-on-Chips provides designers with a variety of design alternatives. In addition, the need to customize the system ar...
Kanishka Lahiri, Sujit Dey, Anand Raghunathan
VLSID
2001
IEEE
184views VLSI» more  VLSID 2001»
15 years 10 months ago
Battery Life Estimation of Mobile Embedded Systems
Since battery life directly impacts the extent and duration of mobility, one of the key considerations in the design of a mobile embedded system should be to maximize the energy d...
Debashis Panigrahi, Sujit Dey, Ramesh R. Rao, Kani...
ICCD
2007
IEEE
322views Hardware» more  ICCD 2007»
15 years 6 months ago
Voltage drop reduction for on-chip power delivery considering leakage current variations
In this paper, we propose a novel on-chip voltage drop reduction technique for on-chip power delivery networks of VLSI systems in the presence of variational leakage current sourc...
Jeffrey Fan, Ning Mi, Sheldon X.-D. Tan
ICCD
2006
IEEE
104views Hardware» more  ICCD 2006»
15 years 6 months ago
Guiding Architectural SRAM Models
— Caches, block memories, predictors, state tables, and other forms of on-chip memory are continuing to consume a greater portion of processor designs with each passing year. Mak...
Banit Agrawal, Timothy Sherwood
ICCAD
2008
IEEE
170views Hardware» more  ICCAD 2008»
15 years 6 months ago
A polynomial time approximation scheme for timing constrained minimum cost layer assignment
Abstract— As VLSI technology enters the nanoscale regime, interconnect delay becomes the bottleneck of circuit performance. Compared to gate delays, wires are becoming increasing...
Shiyan Hu, Zhuo Li, Charles J. Alpert