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FCCM
2003
IEEE
135views VLSI» more  FCCM 2003»
15 years 2 months ago
Efficient Application Representation for HASTE: Hybrid Architectures with a Single, Transformable Executable
Hybrid architectures, which are composed of a conventional processor closely coupled with reconfigurable logic, seem to combine the advantages of both types of hardware. They pres...
Benjamin A. Levine, Herman Schmit
ISCAS
2003
IEEE
131views Hardware» more  ISCAS 2003»
15 years 2 months ago
Process variation dimension reduction based on SVD
We propose an algorithm based on singular value decomposition (SVD) to reduce the number of process variation variables. With few process variation variables, fault simulation and...
Zhuo Li, Xiang Lu, Weiping Shi
85
Voted
ISCAS
2003
IEEE
189views Hardware» more  ISCAS 2003»
15 years 2 months ago
Bio-inspired optical flow circuits for the visual guidance of micro air vehicles
In 1986, Franceschini et al. built an optronic velocity sensor [11], the principle of which was based on the findings they had recently made on fly EMDs by performing electrophysio...
Franck Ruffier, Stéphane Viollet, S. Amic, ...
DAC
2003
ACM
15 years 2 months ago
Crosstalk noise in FPGAs
In recent years, due to rapid advances in VLSI manufacturing technology capable of packing more and more devices and wires on a chip, crosstalk has emerged as a serious problem af...
Yajun Ran, Malgorzata Marek-Sadowska
ISPD
2003
ACM
133views Hardware» more  ISPD 2003»
15 years 2 months ago
Optimal minimum-delay/area zero-skew clock tree wire-sizing in pseudo-polynomial time
In 21st-Century VLSI design, clocking plays crucial roles for both performance and timing convergence. Due to their non-convex nature, optimal minimum-delay/area zero-skew wire-si...
Jeng-Liang Tsai, Tsung-Hao Chen, Charlie Chung-Pin...