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ISPD
1998
ACM
89views Hardware» more  ISPD 1998»
15 years 1 months ago
Filling and slotting: analysis and algorithms
In very deep-submicron VLSI, certain manufacturing steps – notably optical exposure, resist development and etch, chemical vapor deposition and chemical-mechanical polishing (CM...
Andrew B. Kahng, Gabriel Robins, Anish Singh, Huij...
ICCAD
1997
IEEE
86views Hardware» more  ICCAD 1997»
15 years 1 months ago
Interconnect design for deep submicron ICs
Interconnect has become the dominating factor in determining circuit performance and reliability in deep submicron designs. In this embedded tutorial, we first discuss the trends...
Jason Cong, David Zhigang Pan, Lei He, Cheng-Kok K...
81
Voted
PARA
1998
Springer
15 years 1 months ago
Technologies for Teracomputing: A European Option
Abstract. Ahardware and software environment with performance above 1 Tera ops (teracomputing) is presently required to face the leading computational challenges not only in fundam...
Agostino Mathis
82
Voted
DAC
1997
ACM
15 years 1 months ago
More Practical Bounded-Skew Clock Routing
: Academic clock routing research results has often had limited impact on industry practice, since such practical considerations as hierarchical buffering, rise-time and overshoot ...
Andrew B. Kahng, Chung-Wen Albert Tsao
EURODAC
1994
IEEE
127views VHDL» more  EURODAC 1994»
15 years 1 months ago
Optimal equivalent circuits for interconnect delay calculations using moments
In performance-driven interconnect design, delay estimators are used to determine both the topology and the layout of good routing trees. We address the class of moment-matching, ...
Sudhakar Muddu, Andrew B. Kahng