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VLSID
2007
IEEE
98views VLSI» more  VLSID 2007»
15 years 10 months ago
Power Reduction in VLIW Processor with Compiler Driven Bypass Network
Neeraj Goel, Anshul Kumar, Preeti Ranjan Panda
VLSID
2007
IEEE
112views VLSI» more  VLSID 2007»
15 years 10 months ago
Synthesizing "Verification Aware" Models: Why and How?
Malay K. Ganai, Akira Mukaiyama, Aarti Gupta, Kazu...
VLSID
2007
IEEE
127views VLSI» more  VLSID 2007»
15 years 10 months ago
Scalable techniques and tools for reliability analysis of large circuits
Debayan Bhaduri, Sandeep K. Shukla, Paul Graham, M...
VLSID
2006
IEEE
111views VLSI» more  VLSID 2006»
15 years 10 months ago
An Area Efficient Mixed-Signal Test Architecture for Systems-on-a-Chip
Hari Vijay Venkatanarayanan, Michael L. Bushnell