This paper proposes a new fault coverage estimation model which can be used in the early stage of VLSI design. The fault coverage model is an exponentially decaying function with ...
— This paper presents a number of new high-radix ripple-carry adder designs based on Ling’s addition technique and a recently-published expansion thereof. The proposed adders a...
– This paper presents a high speed VLSI implementation of wavelet and golay error control codes. The design has been fabricated by MOSIS in a TSMC 0.25 µm CMOS process. Experime...
In this paper a review of development of manpower in VLSI in India is attempted. In the last decade of the 20th Century, rapid strides have been done in Micro-Electronics in India...