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GLVLSI
1999
IEEE
92views VLSI» more  GLVLSI 1999»
15 years 2 months ago
Fault Coverage Estimation for Early Stage of VLSI Design
This paper proposes a new fault coverage estimation model which can be used in the early stage of VLSI design. The fault coverage model is an exponentially decaying function with ...
Von-Kyoung Kim, Tom Chen, Mick Tegethoff
FCS
2006
14 years 11 months ago
VLSI Layout of Benes Networks
Paul Manuel, Kalim Qureshi, Albert William, Albert...
ARITH
2011
IEEE
13 years 9 months ago
Fast Ripple-Carry Adders in Standard-Cell CMOS VLSI
— This paper presents a number of new high-radix ripple-carry adder designs based on Ling’s addition technique and a recently-published expansion thereof. The proposed adders a...
Neil Burgess
ASPDAC
2004
ACM
71views Hardware» more  ASPDAC 2004»
15 years 3 months ago
Golay and wavelet error control codes in VLSI
– This paper presents a high speed VLSI implementation of wavelet and golay error control codes. The design has been fabricated by MOSIS in a TSMC 0.25 µm CMOS process. Experime...
Arunkumar Balasundaram, Angelo Pereira, Jun-Cheol ...
MSE
2003
IEEE
116views Hardware» more  MSE 2003»
15 years 3 months ago
Manpower Development in VLSI ni India: A Case Study
In this paper a review of development of manpower in VLSI in India is attempted. In the last decade of the 20th Century, rapid strides have been done in Micro-Electronics in India...
K. C. Shet