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DAC
1999
ACM
15 years 10 months ago
Hypergraph Partitioning for VLSI CAD: Methodology for Heuristic Development, Experimentation and Reporting
We illustrate how technical contributions in the VLSI CAD partitioning literature can fail to provide one or more of: (i) reproducible results and descriptions, (ii) an enabling a...
Andrew E. Caldwell, Andrew B. Kahng, Andrew A. Ken...
DAC
2000
ACM
15 years 10 months ago
Forensic engineering techniques for VLSI CAD tools
The proliferation of the Internet has a ected the business model of almost all semiconductor and VLSI CAD companies that rely on intellectual property (IP) as their main source of...
Darko Kirovski, David T. Liu, Jennifer L. Wong, Mi...
DAC
2001
ACM
15 years 10 months ago
Using Texture Mapping with Mipmapping to Render a VLSI Layout
This paper presents a method of using texture mapping with mipmapping to render a VLSI layout. Texture mapping is used to save already rasterized areas of the layout from frame to...
Jeff Solomon, Mark Horowitz
ICASSP
2008
IEEE
15 years 4 months ago
Automatic synthesis of VLSI architectures for arbitrary lifting-based filter banks and transforms
Recently, the conventional lifting scheme that is widely used for the construction of Wavelets and 2-channel filter banks has been extended to M-channel filter banks (M > 2)....
Ruben Bartholomä, Thomas Greiner, Frank Kesel...
IPPS
2006
IEEE
15 years 3 months ago
Evaluating parallel simulated evolution strategies for VLSI cell placement
Simulated Evolution (SimE) is an evolutionary metaheuristic that has produced results comparable to well established stochastic heuristics such as SA, TS and GA, with shorter runti...
Sadiq M. Sait, Mustafa I. Ali, Ali Mustafa Zaidi