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ISCAS
2003
IEEE
93views Hardware» more  ISCAS 2003»
15 years 3 months ago
A rescheduling and fast pipeline VLSI architecture for lifting-based discrete wavelet transform
In this paper, we propose a fast pipeline VLSI architecture for 1D lifting-based discrete wavelet transform (DWT). This design method merges the filtering steps called the predict...
Bing-Fei Wu, Chung-Fu Lin
ISCAS
2003
IEEE
119views Hardware» more  ISCAS 2003»
15 years 3 months ago
Simulated evolution algorithm for multiobjective VLSI netlist bi-partitioning
In this paper, the Simulated Evolution algorithm (SimE) is engineered to solve the optimization problem of multi-objective VLSI netlist bi-partitioning. The multi-objective versio...
Sadiq M. Sait, Aiman H. El-Maleh, Rush H. Al-Abuji
FPL
2001
Springer
130views Hardware» more  FPL 2001»
15 years 2 months ago
FPGA-Based Fault Injection Techniques for Fast Evaluation of Fault Tolerance in VLSI Circuits
Designers of safety-critical VLSI systems are asking for effective tools for evaluating and validating their designs. Fault Injection is commonly adopted for this task, and its eff...
Pierluigi Civera, Luca Macchiarulo, Maurizio Rebau...
DATE
2000
IEEE
86views Hardware» more  DATE 2000»
15 years 2 months ago
A New Partitioning Method for Parallel Simulation of VLSI Circuits on Transistor Level
Simulation is still one of the most important subtasks when designing a VLSI circuit. However, more and more elements on a chip increase simulation runtimes. Especially on transis...
Norbert Fröhlich, Volker Gloeckel, Josef Flei...
ASPDAC
1999
ACM
149views Hardware» more  ASPDAC 1999»
15 years 2 months ago
The Hierarchical h-Adaptive 3-D Boundary Element Computation of VLSI Interconnect Capacitance
: In VLSI circuits with deep sub-micron, the parasitic capacitance from interconnect is a very important factor determining circuit performances such as power and time-delay. The B...
Jinsong Hou, Zeyi Wang, Xianlong Hong