2449 search results - page 89 / 490 » VLSI |
145
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IPPS
1999
IEEE
15 years 7 months ago
1999
IEEE
We propose the recursive grid layout scheme for deriving efficient layouts of a variety of hierarchical networks and computing upper bounds on the VLSI area of general hierarchica...
124
Voted
ISPD
1997
ACM
15 years 7 months ago
1997
ACM
In this paper, we study optimal bu er design in high-performance VLSI systems. Speci cally, we design a bu er for a given load such that chip area and power dissipation are minima...
119
Voted
ICCAD
1994
IEEE
15 years 7 months ago
1994
IEEE
We present an improved data model that reflects the whole VLSI design process including bottom-up and topdown design phases. The kernel of the model is a static version concept th...
115
Voted
VLSID
1993
IEEE
15 years 7 months ago
1993
IEEE
An area-eficzent systolic architecture for realtime, programmable-coeBcient jinite impulse response (FIR)filters is presented. A technique called pipelined clustering is introduce...
122
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ICCAD
1995
IEEE
15 years 7 months ago
1995
IEEE
Pad assignment with signal integrity optimization is very important for high-speed VLSI design. In this paper, an efficient method is proposed to effectively minimize both simulta...