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SIGCOMM
1995
ACM
15 years 7 months ago
Pipelined Memory Shared Buffer for VLSI Switches
ABSTRACT: Switch chips are building blocks for computer and communication systems. Switches need internal buffering, because of output contention; shared buffering is known to perf...
Manolis Katevenis, Panagiota Vatsolaki, Aristides ...
152
Voted
NIPS
2003
15 years 4 months ago
A Mixed-Signal VLSI for Real-Time Generation of Edge-Based Image Vectors
A mixed-signal image filtering VLSI has been developed aiming at real-time generation of edge-based image vectors for robust image recognition. A four-stage asynchronous median de...
Masakazu Yagi, Hideo Yamasaki, Tadashi Shibata
96
Voted
IJCV
1998
81views more  IJCV 1998»
15 years 3 months ago
Estimating the Focus of Expansion in Analog VLSI
In the course of designing an integrated system for locating the focus of expansion (FOE) from a sequence of images taken while a camera is translating, a variety of direct motion ...
Ignacio S. McQuirk, Berthold K. P. Horn, Hae-Seung...
ISCAS
2011
IEEE
288views Hardware» more  ISCAS 2011»
14 years 7 months ago
Multi-layer parallel decoding algorithm and vlsi architecture for quasi-cyclic LDPC codes
—We propose a multi-layer parallel decoding algorithm and VLSI architecture for decoding of structured quasi-cyclic low-density parity-check codes. In the conventional layered de...
Yang Sun, Guohui Wang, Joseph R. Cavallaro
VLSID
2002
IEEE
95views VLSI» more  VLSID 2002»
16 years 3 months ago
A Novel Method to Improve the Test Efficiency of VLSI Tests
This paper considers reducing the cost of test application by permuting test vectors to improve their defect coverage. Algorithms for test reordering are developed with the goal o...
Hailong Cui, Sharad C. Seth, Shashank K. Mehta