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ISCAS
2007
IEEE
106views Hardware» more  ISCAS 2007»
15 years 9 months ago
Regularized Frequency Domain Equalization Algorithm and its VLSI Implementation
Abstract— Approximation of Toeplitz matrices with circulant matrices is a well-known approach to reduce the computational complexity of linear equalizers. This paper presents a n...
Andreas Burg, Simon Haene, Wolfgang Fichtner, Mark...
115
Voted
ISCAS
2006
IEEE
124views Hardware» more  ISCAS 2006»
15 years 9 months ago
Noise Effects on Performance of Signal Detection in an Analog VLSI Resonate-And Fire Neuron
In this paper, we present analog VLSI implementation of a resonate-and-fire neuron (RFN) model, and then consider noise effects on its performance of signal detection. The RFN ci...
Kazuki Nakada, Jun Igarashi, A. Tetsuya, Hatsuo Ha...
106
Voted
ISCAS
2005
IEEE
115views Hardware» more  ISCAS 2005»
15 years 9 months ago
VLSI architecture based on packet data transfer scheme and its application
Abstract— Packet data transfer scheme is introduced for intrachip data transfer to solve an interconnection problem. Double transmission lines are provided as a platform of the m...
Yuya Homma, Michitaka Kameyama, Yoshichika Fujioka...
ISCAS
2005
IEEE
187views Hardware» more  ISCAS 2005»
15 years 9 months ago
New cost-effective VLSI implementation of multiplierless FIR filter using common subexpression elimination
Abstract— In this paper, we propose a novel common subexpresson elimination (CSE) method to be used for VLSI design of multiplierless finite impulse response (FIR) filter with ...
Yasuhiro Takahashi, Michio Yokoyama
ISCAS
1993
IEEE
125views Hardware» more  ISCAS 1993»
15 years 7 months ago
A VLSI Implementation of a Cascade Viterbi Decoder with Traceback
- A novel VLSI implementation of the Viterbi algorithm based on a cascade architecture is presented. Survivor sequence memory management is implemented using a new single read poin...
Gennady Feygin, Paul Chow, P. Glenn Gulak, John Ch...