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112
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TC
2002
15 years 3 months ago
Architectures and VLSI Implementations of the AES-Proposal Rijndael
Two architectures and VLSI implementations of the AES Proposal, Rijndael, are presented in this paper. These alternative architectures are operated both for encryption and decrypti...
Nicolas Sklavos, Odysseas G. Koufopavlou
164
Voted
ISPD
2005
ACM
188views Hardware» more  ISPD 2005»
15 years 9 months ago
A semi-persistent clustering technique for VLSI circuit placement
Placement is a critical component of today's physical synthesis flow with tremendous impact on the final performance of VLSI designs. However, it accounts for a significant p...
Charles J. Alpert, Andrew B. Kahng, Gi-Joon Nam, S...
137
Voted
EURODAC
1994
IEEE
209views VHDL» more  EURODAC 1994»
15 years 7 months ago
MOS VLSI circuit simulation by hardware accelerator using semi-natural models
- The accelerator is destined to circuit-level simulation of digital and analog/digital MOS VLSI'c containing of up to 100 thousand transistors (with 16 Mb RAM host-machine). ...
Victor V. Denisenko
POPL
2007
ACM
16 years 3 months ago
Geometry of synthesis: a structured approach to VLSI design
We propose a new technique for hardware synthesis from higherorder functional languages with imperative features based on Reynolds's Syntactic Control of Interference. The re...
Dan R. Ghica
108
Voted
ICCAD
2005
IEEE
110views Hardware» more  ICCAD 2005»
16 years 10 days ago
Performance analysis of carbon nanotube interconnects for VLSI applications
The work in this paper analyses the applicability of carbon nanotube (CNT) bundles as interconnects for VLSI circuits, while taking into account the practical limitations in this ...
Navin Srivastava, Kaustav Banerjee