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    ISCAS
    2008
    IEEE
    136views Hardware» more  ISCAS 2008»
    VLSI architecture for data-reduced steering matrix feedback in MIMO systems
    15 years 9 months ago
    VLSI architecture for data-reduced steering matrix feedback in MIMO systems
    Download  www.iis.ee.ethz.ch
    Abstract— Beamforming (BF) for multiple-input multipleoutput (MIMO) wireless communications systems can improve the error rate performance by spatial separation of the transmitte...
    Christoph Studer, Peter Luethi, Wolfgang Fichtner
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    122
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    IWANN
    2007
    Springer
    126views Neural Networks» more  IWANN 2007»
    Interconnecting VLSI Spiking Neural Networks Using Isochronous Connections
    15 years 9 months ago
    Interconnecting VLSI Spiking Neural Networks Using Isochronous Connections
    Download  www.kip.uni-heidelberg.de
    This paper presents a network architecture to interconnect mixed-signal VLSI1 integrate-and-fire neural networks in a way that the timing of the neural network data is preserved. ...
    Stefan Philipp, Andreas Grübl, Karlheinz Meie...
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    129
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    IJCNN
    2006
    IEEE
    88views Neural Networks» more  IJCNN 2006»
    Implementing Synaptic Plasticity in a VLSI Spiking Neural Network Model
    15 years 9 months ago
    Implementing Synaptic Plasticity in a VLSI Spiking Neural Network Model
    Download  www.kip.uni-heidelberg.de
    — This paper describes an area-efficient mixed-signal implementation of synapse-based long term plasticity realized in a VLSI1 model of a spiking neural network. The artificial...
    Johannes Schemmel, Andreas Grübl, Karlheinz M...
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    ISCAS
    2006
    IEEE
    94views Hardware» more  ISCAS 2006»
    Relaxed tree search MIMO signal detection algorithm design and VLSI implementation
    15 years 9 months ago
    Relaxed tree search MIMO signal detection algorithm design and VLSI implementation
    Download  www.ecse.rpi.edu
    Abstract— This paper presents an implementation-oriented breadthfirst tree search MIMO detector design solution. Techniques at algorithm and VLSI architecture levels are develop...
    Sizhong Chen, Tong Zhang, M. Goel
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    ISCAS
    2005
    IEEE
    113views Hardware» more  ISCAS 2005»
    On the robustness of an analog VLSI implementation of a time encoding machine
    15 years 9 months ago
    On the robustness of an analog VLSI implementation of a time encoding machine
    Download  www.ee.columbia.edu
    Abstract— Time encoding is a mechanism for representing the information contained in a continuous time, bandlimited, analog signal as the zero-crossings of a binary signal. Time ...
    Peter R. Kinget, Aurel A. Lazar, Laszlo T. Toth
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