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» Validating High-Level Synthesis
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67
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VLSID
2003
IEEE
91views VLSI» more  VLSID 2003»
16 years 11 hour ago
High Level Modeling and Validation Methodologies for Embedded Systems: Bridging the Productivity Gap
Sandeep K. Shukla, Jean-Pierre Talpin, Stephen A. ...
TVLSI
2008
140views more  TVLSI 2008»
14 years 11 months ago
A Novel Mutation-Based Validation Paradigm for High-Level Hardware Descriptions
We present a Mutation-based Validation Paradigm (MVP) technology that can handle complete high-level microprocessor implementations and is based on explicit design error modeling, ...
Jorge Campos, Hussain Al-Asaad
BICA
2010
14 years 6 months ago
Validating a High Level Behavioral Representation Language (HERBAL): A Docking Study for ACT-R
We present a docking study for Herbal, a high-level behavioral representation language based on the problem space computational model. This study docks an ACT-R model created with ...
Changkun Zhao, Jaehyon Paik, Jonathan H. Morgan, F...
98
Voted
MTV
2006
IEEE
97views Hardware» more  MTV 2006»
15 years 5 months ago
Circuit Profiling Mechanisms for High-Level {ATPG}
—Our Mutation-based Validation Paradigm (MVP) is a validation environment for high-level microprocessor implementations. To be able to efficiently generate test sequences, we nee...
Jorge Campos, Hussain Al-Asaad