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» Validating High-Level Synthesis
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EUROMICRO
2002
IEEE
15 years 4 months ago
A Sum of Absolute Differences Implementation in FPGA Hardware
In this paper, we propose a new hardware unit that performs a 16 × 1 SAD operation. The hardware unit is intended to augment a general-purpose core. Further, we show that the 16 ...
Stephan Wong, Stamatis Vassiliadis, Sorin Cotofana
ICAD
2004
15 years 1 months ago
Decoupled Loudness and Range Control for a Source Located Within a Small Virtual Acoustic Environment
For headphone-based spatial auditory display systems, binaural synthesis of sound localization cues typically use source reproduction level as the primary control for source range...
William L. Martens
ICASSP
2009
IEEE
15 years 6 months ago
Control of prosodic focus in corpus-based generation of fundamental frequency contours of Japanese based on the generation proce
A total corpus-based process of generating prosodic features from text is developed. The process first predicts pauses and phone durations, and then generates F0 contours. Since F...
Keiko Ochi, Keikichi Hirose, Nobuaki Minematsu
HICSS
2007
IEEE
97views Biometrics» more  HICSS 2007»
15 years 6 months ago
Implementation-Oriented Secure Architectures
We propose a framework for constructing secure systems at the architectural level. This framework is composed of an implementation-oriented formalization of a system’s architect...
Daniel Conte de Leon, Jim Alves-Foss, Paul W. Oman
ESTIMEDIA
2004
Springer
15 years 5 months ago
A queuing-theoretic performance model for context-flow system-on-chip platforms
Abstract—Few analytical performance models that relate performance figure of merit to architectural design decisions are reported in recent studies of network-on-chip, which pre...
Rami Beidas, Jianwen Zhu