1663 search results - page 121 / 333 » Validation and Verification of Simulation Models |
126
Voted
ECCV
2008
Springer
16 years 5 months ago
2008
Springer
This paper presents an approach for modeling landmark sites such as the Statue of Liberty based on large-scale contaminated image collections gathered from the Internet. Our system...
134
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DSD
2009
IEEE
15 years 1 months ago
2009
IEEE
Several traditional VHDL fault injection mechanisms like mutants or saboteurs have been adapted to SystemC model descriptions. The main drawback of these approaches is the necessi...
146
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CAISE
2006
Springer
15 years 7 months ago
2006
Springer
The quest for designing secure and trusted software has led to refined Software Engineering methodologies that rely on tools to support the design process. Automated reasoning mech...
119
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CSFW
2005
IEEE
15 years 9 months ago
2005
IEEE
We study an automatic technique for the verification of cryptographic protocols based on a Horn clause model of the protocol. This technique yields proofs valid for an unbounded ...
118
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EURODAC
1995
IEEE
15 years 7 months ago
1995
IEEE
The behaviour of a real-time system can be validated at the system level by means of a real-time operating system model in a VHDL simulation environment. The model consists of the...