1663 search results - page 185 / 333 » Validation and Verification of Simulation Models |
140
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ICSE
2010
IEEE-ACM
15 years 6 months ago
2010
IEEE-ACM
Typestate analysis determines whether a program violates a set of finite-state properties. Because the typestate-analysis problem is statically undecidable, researchers have propo...
130
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ICCD
2004
IEEE
16 years 1 months ago
2004
IEEE
A cache access time model, PRACTICS (PRedictor of Access and Cycle TIme for Cache Stack), has been developed to optimize the memory array architecture for the minimum access and c...
134
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INFOCOM
2006
IEEE
15 years 10 months ago
2006
IEEE
— This paper presents an analytical model of steady state throughput of the Slow-but-Steady variant of TCP NewReno as a function of loss event rate, average number of segments lo...
123
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DATE
2003
IEEE
15 years 9 months ago
2003
IEEE
A primary goal of high-level modeling is to efficiently explore a broad design space, converging on an optimal or near-optimal system architecture before moving to a more detaile...
138
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ACSW
2007
15 years 5 months ago
2007
This paper addresses the problem of performance analysis based on communication modelling of largescale heterogeneous distributed systems with emphases on enterprise grid computin...