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» Validation and Verification of Simulation Models
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BMCBI
2010
176views more  BMCBI 2010»
15 years 4 months ago
Reverse engineering gene regulatory network from microarray data using linear time-variant model
nd: Gene regulatory network is an abstract mapping of gene regulations in living cells that can help to predict the system behavior of living organisms. Such prediction capability...
Mitra Kabir, Nasimul Noman, Hitoshi Iba
WSC
1998
15 years 5 months ago
Customer Interfacing - Lessons Learned
Customer interfacing is the process through which one works with and relates to their customer. Often in the technical world, modelers find it easier to interface with computers r...
David M. Ferrin, Richard P. Lavecchia
VLSID
2008
IEEE
128views VLSI» more  VLSID 2008»
16 years 4 months ago
Addressing the Challenges of Synchronization/Communication and Debugging Support in Hardware/Software Cosimulation
With increasing adoption of Electronic System Level (ESL) tools, effective design and validation time has reduced to a considerable extent. Cosimulation is found to be a principal...
Banit Agrawal, Timothy Sherwood, Chulho Shin, Simo...
DAC
2003
ACM
16 years 5 months ago
Support vector machines for analog circuit performance representation
The use of Support Vector Machines (SVMs) to represent the performance space of analog circuits is explored. In abstract terms, an analog circuit maps a set of input design parame...
Fernando De Bernardinis, Michael I. Jordan, Albert...
ASPDAC
2006
ACM
137views Hardware» more  ASPDAC 2006»
15 years 10 months ago
Parameterized block-based non-gaussian statistical gate timing analysis
As technology scales down, timing verification of digital integrated circuits becomes an increasingly challenging task due to the gate and wire variability. Therefore, statistical...
Soroush Abbaspour, Hanif Fatemi, Massoud Pedram