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» Validation and Verification of Simulation Models
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TC
1998
14 years 9 months ago
Abstraction Techniques for Validation Coverage Analysis and Test Generation
ion Techniques for Validation Coverage Analysis and Test Generation Dinos Moundanos, Jacob A. Abraham, Fellow, IEEE, and Yatin V. Hoskote —The enormous state spaces which must be...
Dinos Moundanos, Jacob A. Abraham, Yatin Vasant Ho...
DAC
2006
ACM
15 years 10 months ago
Prototyping a fault-tolerant multiprocessor SoC with run-time fault recovery
Modern integrated circuits (ICs) are becoming increasingly complex. The complexity makes it difficult to design, manufacture and integrate these high-performance ICs. The advent o...
Xinping Zhu, Wei Qin
WSC
2001
14 years 11 months ago
Production scheduling validity in high level supply chain models
Although they focus on the big picture, high level supply chain models cannot gloss over the capacity of production nodes to meet production allocations. Capacity is not simply a ...
David J. Parsons, Richard A. Phelps
SPIN
2004
Springer
15 years 3 months ago
Validation of UML Models via a Mapping to Communicating Extended Timed Automata
Abstract. We present a technique and a tool for model-checking operational UML models based on a mapping of object oriented UML models into a framework of communicating extended ti...
Iulian Ober, Susanne Graf, Ileana Ober
DATE
2007
IEEE
123views Hardware» more  DATE 2007»
15 years 4 months ago
Clock domain crossing fault model and coverage metric for validation of SoC design
Multiple asynchronous clock domains have been increasingly employed in System-on-Chip (SoC) designs for different I/O interfaces. Functional validation is one of the most expensiv...
Yi Feng 0002, Zheng Zhou, Dong Tong, Xu Cheng