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» Validation and Verification of Simulation Models
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103
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ASYNC
2002
IEEE
120views Hardware» more  ASYNC 2002»
15 years 8 months ago
Relative Timing Based Verification of Timed Circuits and Systems
Advanced clock-delayed1 and self-resetting domino circuits are becoming increasingly important design styles in aggressive synchronous as well as asynchronous design. Their design...
Peter A. Beerel, Ken S. Stevens, Hoshik Kim
124
Voted
ISSS
2002
IEEE
125views Hardware» more  ISSS 2002»
15 years 8 months ago
Design Experience of a Chip Multiprocessor Merlot and Expectation to Functional Verification
We have fabricated a Chip Multiprocessor prototype code-named Merlot to proof our novel speculative multithreading architecture. On Merlot, multiple threads provide wider issue wi...
Satoshi Matsushita
126
Voted
ICMLA
2008
15 years 5 months ago
Towards On-line Treatment Verification Using cine EPID for Hypofractionated Lung Radiotherapy
We propose a novel approach for on-line treatment verification using cine EPID (Electronic Portal Imaging Device) images for hypofractionated lung radiotherapy based on a machine ...
Xiaoli Tang, Tong Lin, Steve B. Jiang
147
Voted
IDEAL
2010
Springer
15 years 1 months ago
Trajectory Based Behavior Analysis for User Verification
Many of our activities on computer need a verification step for authorized access. The goal of verification is to tell apart the true account owner from intruders. We propose a gen...
Hsing-Kuo Pao, Hong-Yi Lin, Kuan-Ta Chen, Junaidil...
143
Voted
AINA
2003
IEEE
15 years 7 months ago
Formal Verification of Condition Data Flow Diagrams for Assurance of Correct Network Protocols
Condition Data Flow Diagrams (CDFDs) are a formalized notation resulting from the integration of Yourdon Data Flow Diagrams, Petri Nets, and pre-post notation. They are used in th...
Shaoying Liu