363 search results - page 3 / 73 » Validation coverage analysis for complex digital designs |
DATE
2007
IEEE
14 years 23 days ago
2007
IEEE
This paper proposes an innovative methodology to perform and validate a Failure Mode and Effects Analysis (FMEA) at System-on-Chip (SoC) level. This is done in compliance with the...
ITC
1998
IEEE
13 years 10 months ago
1998
IEEE
New methodologies based on functional testing and built-in self-test can narrow the gap between necessary solutions and existing techniques for processor validation and testing. W...
HPCA
2009
IEEE
14 years 7 months ago
2009
IEEE
The number of functional errors escaping design verification and being released into final silicon is growing, due to the increasing complexity and shrinking production schedules ...
IFIP
2001
Springer
13 years 11 months ago
2001
Springer
— Semi-formal verification based on symbolic simulation offers a good compromise between formal model checking and numerical simulation. The generation of functional test vector...
DATE
2006
IEEE
14 years 14 days ago
2006
IEEE
Practitioners of formal property verification often work around the capacity limitations of formal verification tools by breaking down properties into smaller properties that ca...