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ICS
2009
Tsinghua U.
15 years 4 months ago
Performance modeling and automatic ghost zone optimization for iterative stencil loops on GPUs
Iterative stencil loops (ISLs) are used in many applications and tiling is a well-known technique to localize their computation. When ISLs are tiled across a parallel architecture...
Jiayuan Meng, Kevin Skadron
DATE
2009
IEEE
178views Hardware» more  DATE 2009»
15 years 4 months ago
ORION 2.0: A fast and accurate NoC power and area model for early-stage design space exploration
As industry moves towards many-core chips, networks-on-chip (NoCs) are emerging as the scalable fabric for interconnecting the cores. With power now the first-order design constr...
Andrew B. Kahng, Bin Li, Li-Shiuan Peh, Kambiz Sam...
DSD
2009
IEEE
144views Hardware» more  DSD 2009»
15 years 4 months ago
Composable Resource Sharing Based on Latency-Rate Servers
Abstract—Verification of application requirements is becoming a bottleneck in system-on-chip design, as the number of applications grows. Traditionally, the verification comple...
Benny Akesson, Andreas Hansson, Kees Goossens
INFOCOM
2009
IEEE
15 years 4 months ago
Scalar Prefix Search: A New Route Lookup Algorithm for Next Generation Internet
Currently, the increasing rate of routing lookups in Internet routers, the large number of prefixes and also the transition from IPV4 to IPV6, have caused Internet designers to pro...
Mohammad Behdadfar, Hossein Saidi, Hamid Alaei, Ba...
ASIACRYPT
2009
Springer
15 years 4 months ago
A Modular Design for Hash Functions: Towards Making the Mix-Compress-Mix Approach Practical
The design of cryptographic hash functions is a very complex and failure-prone process. For this reason, this paper puts forward a completely modular and fault-tolerant approach to...
Anja Lehmann, Stefano Tessaro