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ASPDAC
2004
ACM
106views Hardware» more  ASPDAC 2004»
15 years 3 months ago
A novel memory size model for variable-mapping in system level design
— It is predicted that 70% of the chip area will be occupied by memories in future system-onchips. The minimization of on-chip memory hence becomes increasingly important for cos...
Lukai Cai, Haobo Yu, Daniel Gajski
ASPDAC
2009
ACM
122views Hardware» more  ASPDAC 2009»
15 years 4 months ago
Tolerating process variations in high-level synthesis using transparent latches
—Considering process variability at the behavior synthesis level is necessary, because it makes some instances of function units slower and others faster, resulting in unbalanced...
Yibo Chen, Yuan Xie
ASPDAC
1995
ACM
108views Hardware» more  ASPDAC 1995»
15 years 1 months ago
Synthesis-for-testability using transformations
- We address the problem of transforming a behavioral specification so that synthesis of a testable implementation from the new specification requires significantly less area and ...
Miodrag Potkonjak, Sujit Dey, Rabindra K. Roy
SBCCI
2009
ACM
187views VLSI» more  SBCCI 2009»
15 years 2 months ago
Design of low complexity digital FIR filters
The multiplication of a variable by multiple constants, i.e., the multiple constant multiplications (MCM), has been a central operation and performance bottleneck in many applicat...
Levent Aksoy, Diego Jaccottet, Eduardo Costa
JSAC
2006
100views more  JSAC 2006»
14 years 9 months ago
Backbone Topology Synthesis for Multiradio Mesh Networks
Wireless local area network (WLAN) systems are widely implemented today to provide hot-spot coverage. Operated typically in an infrastructure mode, each WLAN is managed by an acces...
Laura Huei-jiun Ju, Izhak Rubin