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TCAD
2008
172views more  TCAD 2008»
14 years 9 months ago
General Methodology for Soft-Error-Aware Power Optimization Using Gate Sizing
Power consumption has emerged as the premier and most constraining aspect in modern microprocessor and application-specific designs. Gate sizing has been shown to be one of the mos...
Foad Dabiri, Ani Nahapetian, Tammara Massey, Miodr...
75
Voted
ASYNC
2007
IEEE
131views Hardware» more  ASYNC 2007»
15 years 3 months ago
High Rate Wave-pipelined Asynchronous On-chip Bit-serial Data Link
A high data rate asynchronous bit-serial link for long-range on-chip communication is presented. The data bit cycle time is equal to a single gate delay, enabling 67Gbps throughpu...
Rostislav (Reuven) Dobkin, Yevgeny Perelman, Tuvia...
NOCS
2008
IEEE
15 years 3 months ago
Network Simplicity for Latency Insensitive Cores
In this paper we examine a latency insensitive network composed of very fast and simple circuits that connects SoC cores that are also latency insensitive, de-synchronized, or asy...
Daniel Gebhardt, JunBok You, W. Scott Lee, Kenneth...
HPCA
2011
IEEE
14 years 1 months ago
Mercury: A fast and energy-efficient multi-level cell based Phase Change Memory system
― Phase Change Memory (PCM) is one of the most promising technologies among emerging non-volatile memories. PCM stores data in crystalline and amorphous phases of the GST materia...
Madhura Joshi, Wangyuan Zhang, Tao Li
ICCAD
2006
IEEE
103views Hardware» more  ICCAD 2006»
15 years 6 months ago
A statistical framework for post-silicon tuning through body bias clustering
Adaptive body biasing (ABB) is a powerful technique that allows post-silicon tuning of individual manufactured dies such that each die optimally meets the delay and power constrai...
Sarvesh H. Kulkarni, Dennis Sylvester, David Blaau...