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» Variation-Aware Fault Modeling
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183
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DAC
2006
ACM
16 years 4 months ago
Prototyping a fault-tolerant multiprocessor SoC with run-time fault recovery
Modern integrated circuits (ICs) are becoming increasingly complex. The complexity makes it difficult to design, manufacture and integrate these high-performance ICs. The advent o...
Xinping Zhu, Wei Qin
149
Voted
DAC
2006
ACM
15 years 5 months ago
Systematic software-based self-test for pipelined processors
Software-based self-test (SBST) has recently emerged as an effective methodology for the manufacturing test of processors and other components in systems-on-chip (SoCs). By moving ...
Mihalis Psarakis, Dimitris Gizopoulos, Miltiadis H...
135
Voted
ICCAD
2007
IEEE
110views Hardware» more  ICCAD 2007»
16 years 16 days ago
A hybrid scheme for compacting test responses with unknown values
This paper presents a hybrid compaction scheme for test responses containing unknown values, which consists of a space compactor and an unknown-blocking Multiple Input Signature R...
Mango Chia-Tso Chao, Kwang-Ting Cheng, Seongmoon W...
106
Voted
ATS
2009
IEEE
113views Hardware» more  ATS 2009»
15 years 10 months ago
Deterministic Algorithms for ATPG under Leakage Constraints
—Measuring the steady state leakage current (IDDQ) is very successful in detecting faults not discovered by standard fault models. But vector dependencies of IDDQ decrease the re...
Gorschwin Fey
127
Voted
ETS
2006
IEEE
93views Hardware» more  ETS 2006»
15 years 9 months ago
Retention-Aware Test Scheduling for BISTed Embedded SRAMs
In this paper we address the test scheduling problem for Builtin Self-tested (BISTed) embedded SRAMs (e-SRAMs) when Data Retention Faults (DRFs) are considered. The proposed test ...
Qiang Xu, Baosheng Wang, F. Y. Young