Detection of defective pixels that develop on-line is a vital part of fault tolerant schemes for repairing imagers during operation. This paper presents a new algorithm for the id...
Glenn H. Chapman, Israel Koren, Zahava Koren, Jozs...
The clock rate of modern chips is still increasing and at the same time the gate size decreases. As a result, already slight variations during the production process may cause a f...
The ability to predict which files in a large software system are most likely to contain the largest numbers of faults in the next release can be a very valuable asset. To accomp...
Thomas J. Ostrand, Elaine J. Weyuker, Robert M. Be...
Most memory test algorithms are optimized tests for a particular memory technology and a particular set of fault models, under the assumption that the memory is bit-oriented; i.e....
Using formal verification for designing hardware designs free from logic design bugs has been an active area of research since the last 15 years. Technology has matured and we hav...