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VTS
2003
IEEE
89views Hardware» more  VTS 2003»
15 years 2 months ago
Detecting Intra-Word Faults in Word-Oriented Memories
This paper improves upon the state of the art in testing word oriented memories. It first presents a complete set of fault models for intra-word coupling faults. Then, it establi...
Said Hamdioui, A. J. van de Goor, Mike Rodgers
DATE
2002
IEEE
99views Hardware» more  DATE 2002»
15 years 2 months ago
Gate Level Fault Diagnosis in Scan-Based BIST
A gate level, automated fault diagnosis scheme is proposed for scan-based BIST designs. The proposed scheme utilizes both fault capturing scan chain information and failing test v...
Ismet Bayraktaroglu, Alex Orailoglu
DFT
2003
IEEE
83views VLSI» more  DFT 2003»
15 years 2 months ago
Yield Modeling and Analysis of a Clockless Asynchronous Wave Pipeline with Pulse Faults
This paper proposes a new fault model and its modeling and analysis methods in a clockless asynchronous wave pipeline for extensive yield evaluation and assurance. It is highly de...
T. Feng, Nohpill Park, Yong-Bin Kim, Vincenzo Piur...
DFT
2003
IEEE
114views VLSI» more  DFT 2003»
15 years 2 months ago
CodSim -- A Combined Delay Fault Simulator
Delay faults are an increasingly important test challenge. Traditional delay fault models are incomplete in that they only model a subset of delay defect behaviors. To solve this ...
Wangqi Qiu, Xiang Lu, Zhuo Li, D. M. H. Walker, We...
ICCAD
2006
IEEE
134views Hardware» more  ICCAD 2006»
15 years 6 months ago
A delay fault model for at-speed fault simulation and test generation
We describe a transition fault model, which is easy to simulate under test sequences that are applied at-speed, and provides a target for the generation of at-speed test sequences...
Irith Pomeranz, Sudhakar M. Reddy