This paper improves upon the state of the art in testing word oriented memories. It first presents a complete set of fault models for intra-word coupling faults. Then, it establi...
A gate level, automated fault diagnosis scheme is proposed for scan-based BIST designs. The proposed scheme utilizes both fault capturing scan chain information and failing test v...
This paper proposes a new fault model and its modeling and analysis methods in a clockless asynchronous wave pipeline for extensive yield evaluation and assurance. It is highly de...
T. Feng, Nohpill Park, Yong-Bin Kim, Vincenzo Piur...
Delay faults are an increasingly important test challenge. Traditional delay fault models are incomplete in that they only model a subset of delay defect behaviors. To solve this ...
Wangqi Qiu, Xiang Lu, Zhuo Li, D. M. H. Walker, We...
We describe a transition fault model, which is easy to simulate under test sequences that are applied at-speed, and provides a target for the generation of at-speed test sequences...