226 search results - page 36 / 46 » Variation-tolerant circuits: circuit solutions and technique... |
140
Voted
ISPD
2005
ACM
15 years 7 months ago
2005
ACM
The sustained progress of VLSI technology has altered the landscape of routing which is a major physical design stage. For timing driven routings, traditional approaches which con...
94
Voted
DAC
2005
ACM
16 years 2 months ago
2005
ACM
Placement migration is the movement of cells within an existing placement to address a variety of post-placement design closure issues, such as timing, routing congestion, signal ...
124
click to vote
VLSID
2002
IEEE
16 years 2 months ago
2002
IEEE
IDDQ testing has been used as a test technique to supplement voltage testing of CMOS chips. The idea behind IDDQ testing is to declare a chip as faulty if the steady-state current...
112
Voted
DATE
2009
IEEE
15 years 8 months ago
2009
IEEE
— Clock-gating and power-gating have proven to be very effective solutions for reducing dynamic and static power, respectively. The two techniques may be coupled in such a way th...
111
Voted
ISPD
2005
ACM
15 years 7 months ago
2005
ACM
In this paper, we present a hierarchical ratio partitioning based placement algorithm for large-scale mixed-size designs. The placement algorithm consists of three steps: global p...