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LCTRTS
2009
Springer
15 years 6 months ago
Guaranteeing instruction fetch behavior with a lookahead instruction fetch engine (LIFE)
Instruction fetch behavior has been shown to be very regular and predictable, even for diverse application areas. In this work, we propose the Lookahead Instruction Fetch Engine (...
Stephen Roderick Hines, Yuval Peress, Peter Gavin,...
IJHPCA
2006
122views more  IJHPCA 2006»
14 years 11 months ago
A New Hardware Monitor Design to Measure Data Structure-Specific Cache Eviction Information
In this paper, we propose a hardware performance monitor that provides support not only for measuring cache misses and the addresses associated with them, but also for determining...
Bryan R. Buck, Jeffrey K. Hollingsworth
RTSS
2008
IEEE
15 years 6 months ago
WCET Analysis of Multi-level Non-inclusive Set-Associative Instruction Caches
With the advent of increasingly complex hardware in realtime embedded systems (processors with performance enhancing features such as pipelines, cache hierarchy, multiple cores), ...
Damien Hardy, Isabelle Puaut
MICRO
2007
IEEE
120views Hardware» more  MICRO 2007»
15 years 6 months ago
Scavenger: A New Last Level Cache Architecture with Global Block Priority
Addresses suffering from cache misses typically exhibit repetitive patterns due to the temporal locality inherent in the access stream. However, we observe that the number of inte...
Arkaprava Basu, Nevin Kirman, Meyrem Kirman, Maina...
ICPADS
2006
IEEE
15 years 5 months ago
A Distributed Algorithm for Sharing Web Cache Disk Capacity
A decentralized game theoretic framework applied to Web caching is discussed. The interaction of multiple clients with a caching server is modeled as a non-cooperative game, in wh...
George Alyfantis, Stathes Hadjiefthymiades, Lazaro...