809 search results - page 26 / 162 » Variations in Cache Behavior |
162
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HPCA
2004
IEEE
16 years 3 days ago
2004
IEEE
Recent research suggests that there are large variations in a cache's spatial usage, both within and across programs. Unfortunately, conventional caches typically employ fixe...
107
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HPCA
2002
IEEE
16 years 3 days ago
2002
IEEE
The increasing performance gap between processors and memory will force future architectures to devote significant resources towards removing and hiding memory latency. The two ma...
ICS
2004
Tsinghua U.
15 years 5 months ago
2004
Tsinghua U.
The growing dominance of wire delays at future technology points renders a microprocessor communication-bound. Clustered microarchitectures allow most dependence chains to execute...
ANCS
2009
ACM
14 years 9 months ago
2009
ACM
This paper proposes a new server architecture EINIC (Enhanced Integrated NIC) for multi-core processors to tackle the mismatch between network speed and host computational capacit...
169
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ICDE
2005
IEEE
16 years 1 months ago
2005
IEEE
Hardware cache behavior is an important factor in the performance of memory-resident, data-intensive systems such as XML filtering engines. A key data structure in several recent ...