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ECRTS
2009
IEEE
14 years 9 months ago
On the Design and Implementation of a Cache-Aware Multicore Real-Time Scheduler
Multicore architectures, which have multiple processing units on a single chip, have been adopted by most chip manufacturers. Most such chips contain on-chip caches that are share...
John M. Calandrino, James H. Anderson
ACMMSP
2005
ACM
106views Hardware» more  ACMMSP 2005»
15 years 5 months ago
Impact of modern memory subsystems on cache optimizations for stencil computations
In this work we investigate the impact of evolving memory system features, such as large on-chip caches, automatic prefetch, and the growing distance to main memory on 3D stencil ...
Shoaib Kamil, Parry Husbands, Leonid Oliker, John ...
CTRSA
2010
Springer
152views Cryptology» more  CTRSA 2010»
15 years 3 months ago
Differential Cache-Collision Timing Attacks on AES with Applications to Embedded CPUs
This paper proposes a new type of cache-collision timing attacks on software implementations of AES. Our major technique is of differential nature and is based on the internal cryp...
Andrey Bogdanov, Thomas Eisenbarth, Christof Paar,...
TPDS
2008
101views more  TPDS 2008»
14 years 11 months ago
An Energy-Oriented Evaluation of Buffer Cache Algorithms Using Parallel I/O Workloads
Power consumption is an important issue for cluster supercomputers as it directly affects running cost and cooling requirements. This paper investigates the memory energy efficienc...
Jianhui Yue, Yifeng Zhu, Zhao Cai
CODES
2010
IEEE
14 years 9 months ago
Dynamic, non-linear cache architecture for power-sensitive mobile processors
Today, mobile smartphones are expected to be able to run the same complex, algorithm-heavy, memory-intensive applications that were originally designed and coded for generalpurpos...
Garo Bournoutian, Alex Orailoglu