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CASES
2001
ACM
15 years 3 months ago
Transparent data-memory organizations for digital signal processors
Today's digital signal processors (DSPs), unlike general-purpose processors, use a non-uniform addressing model in which the primary components of the memory system--the DRAM...
Sadagopan Srinivasan, Vinodh Cuppu, Bruce L. Jacob
CCS
2008
ACM
15 years 1 months ago
Mitigating DNS DoS attacks
This paper considers DoS attacks on DNS wherein attackers flood the nameservers of a zone to disrupt resolution of resource records belonging to the zone and consequently, any of ...
Hitesh Ballani, Paul Francis
SIGMOD
2005
ACM
77views Database» more  SIGMOD 2005»
15 years 12 months ago
On Joining and Caching Stochastic Streams
We consider the problem of joining data streams using limited cache memory, with the goal of producing as many result tuples as possible from the cache. Many cache replacement heu...
Jun Yang 0001, Junyi Xie, Yuguo Chen
ISCA
1997
IEEE
135views Hardware» more  ISCA 1997»
15 years 4 months ago
The Design and Analysis of a Cache Architecture for Texture Mapping
The effectiveness of texture mapping in enhancing the realism of computer generated imagery has made support for real-time texture mapping a critical part of graphics pipelines. D...
Ziyad S. Hakura, Anoop Gupta
ISCA
2010
IEEE
205views Hardware» more  ISCA 2010»
15 years 5 months ago
The virtual write queue: coordinating DRAM and last-level cache policies
In computer architecture, caches have primarily been viewed as a means to hide memory latency from the CPU. Cache policies have focused on anticipating the CPU’s data needs, and...
Jeffrey Stuecheli, Dimitris Kaseridis, David Daly,...