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CAL
2002
14 years 9 months ago
Page-Level Behavior of Cache Contention
Cache misses in small, limited-associativity primary caches very often replace live cache blocks, given the dominance of capacity and conflict misses. Towards motivating novel cach...
Siddhartha V. Tambat, Sriram Vajapeyam
DSD
2009
IEEE
136views Hardware» more  DSD 2009»
15 years 1 months ago
An Evaluation of Behaviors of S-NUCA CMPs Running Scientific Workload
Modern systems are able to put two or more processors on the same die (Chip Multiprocessors, CMP), each with its private caches, while the last level caches can be either private ...
Pierfrancesco Foglia, Francesco Panicucci, Cosimo ...
ADBIS
2004
Springer
124views Database» more  ADBIS 2004»
15 years 2 months ago
Database Caching - Towards a Cost Model for Populating Cache Groups
Web caching keeps single Web objects ready somewhere in caches in the user-to-server path, whereas database caching uses fullfledged database management systems as caches to adapt...
Theo Härder, Andreas Bühmann
ICPP
2008
IEEE
15 years 4 months ago
Taming Single-Thread Program Performance on Many Distributed On-Chip L2 Caches
This paper presents a two-part study on managing distributed NUCA (Non-Uniform Cache Architecture) L2 caches in a future manycore processor to obtain high singlethread program per...
Lei Jin, Sangyeun Cho
MICRO
2007
IEEE
144views Hardware» more  MICRO 2007»
15 years 3 months ago
Process Variation Tolerant 3T1D-Based Cache Architectures
Process variations will greatly impact the stability, leakage power consumption, and performance of future microprocessors. These variations are especially detrimental to 6T SRAM ...
Xiaoyao Liang, Ramon Canal, Gu-Yeon Wei, David Bro...