809 search results - page 60 / 162 » Variations in Cache Behavior |
HIPEAC
2009
Springer
15 years 4 months ago
2009
Springer
Abstract. Technological advances and increasingly complex and dynamic application behavior argue for revisiting mechanisms that adapt logical cache block size to application charac...
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GECCO
2009
Springer
14 years 9 months ago
2009
Springer
Simultaneous Multithreading (SMT) is a technology aimed at improving the throughput of the processor core by applying Instruction Level Parallelism (ILP) and Thread Level Parallel...
VLSID
2008
IEEE
16 years 6 days ago
2008
IEEE
Worst-case execution time (WCET) analysis and, in general, the predictability of real-time applications implemented on multiprocessor systems has been addressed only in very restri...
HIPEAC
2010
Springer
15 years 9 months ago
2010
Springer
Abstract. The shared-cache contention on Chip Multiprocessors causes performance degradation to applications and hurts system fairness. Many previously proposed solutions schedule ...
DATE
2005
IEEE
15 years 5 months ago
2005
IEEE
Utilizing on-chip caches in embedded multiprocessorsystem-on-a-chip (MPSoC) based systems is critical from both performance and power perspectives. While most of the prior work th...