Sciweavers

809 search results - page 6 / 162
» Variations in Cache Behavior
Sort
View
86
Voted
ISCA
2002
IEEE
68views Hardware» more  ISCA 2002»
15 years 4 months ago
Timekeeping in the Memory System: Predicting and Optimizing Memory Behavior
Techniques for analyzing and improving memory referencing behavior continue to be important for achieving good overall program performance due to the ever-increasing performance g...
Zhigang Hu, Margaret Martonosi, Stefanos Kaxiras
PRDC
2006
IEEE
15 years 5 months ago
SEVA: A Soft-Error- and Variation-Aware Cache Architecture
As SRAM devices are scaled down, the number of variation-induced defective memory cells increases rapidly. Combination of ECC, particularly SECDED, with a redundancy technique can...
Luong Dinh Hung, Masahiro Goshima, Shuichi Sakai
86
Voted
HPCA
2002
IEEE
15 years 4 months ago
Non-Vital Loads
As the frequency gap between main memory and modern microprocessor grows, the implementation and efficiency of on-chip caches become more important. The growing latency to memory ...
Ryan Rakvic, Bryan Black, Deepak Limaye, John Paul...
SIGMETRICS
1997
ACM
111views Hardware» more  SIGMETRICS 1997»
15 years 3 months ago
Cache Behavior of Network Protocols
In this paper we present a performance study of memory reference behavior in network protocol processing, using an Internet-based protocol stack implemented in the x-kernel runnin...
Erich M. Nahum, David J. Yates, James F. Kurose, D...