809 search results - page 70 / 162 » Variations in Cache Behavior |
100
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HPCA
2008
IEEE
16 years 6 days ago
2008
IEEE
The trend towards integrating multiple cores on the same die has accentuated the need for larger on-chip caches. Such large caches are constructed as a multitude of smaller cache ...
VEE
2005
ACM
15 years 5 months ago
2005
ACM
Virtual execution environments have become increasingly useful in system implementation, with dynamic translation techniques being an important component for performance-critical ...
112
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CASES
2011
ACM
13 years 11 months ago
2011
ACM
Escalating variations in modern CMOS designs have become a threat to Moore’s law. While previous works have proposed techniques for tolerating variations by trading reliability ...
HPCA
1999
IEEE
15 years 4 months ago
1999
IEEE
We propose Instruction-based Prediction as a means to optimize directory-based cache coherent NUMA shared-memory. Instruction-based prediction is based on observing the behavior o...
SPAA
1990
ACM
15 years 3 months ago
1990
ACM
Multithreading has been proposed as an architectural strategy for tolerating latency in multiprocessors and, through limited empirical studies, shown to offer promise. This paper ...